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Clock Generator for Cavium Processors
ICS8430S07I
DATA SHEET
General Description
The ICS8430S07I is a PLL-based clock generator specifically designed for Cavium Networks SoC HiPerClockSTM processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN3005/CN3010/CN3020 processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the ICS8430S07I supports telecommunication, networking, and storage requirements.
Features
* *
One selectable differential LVPECL output pair for DDR 533/400/667 Six LVCMOS/ LVTTL outputs, 15 typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock references for GbE PHY Selectable external crystal or differential (single-ended) input source Crystal oscillator interface designed for 25MHz, parallel resonant crystal Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.78ps (typical), QD output Output supply: LVPECL - 3.3V Core LVCMOS - Core/Output 3.3V/3.3V 3.3V/2.5V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
ICS
* * * * *
Applications
* *
Systems using CN30XX MIPS64 Broadband Processors Networking, control and storage equipment, including routers, switches, application-aware gateways, triple-play gateways, WLAN and 3G/4G access and aggregation devices, storage arrays, storage networking equipment, servers, and intelligent NICs 802.11 a/b/g/n wireless for home data and multi-media distribution QoS for high quality Voice, Video, and Data Service Next-generation PON, VDSL2, and Cable Networks High-performance NAS Audio/Video Storage and Distribution Consumer Space Media Server
*
* *
VDDO_REF
QREF0
QREF1
QREF2
VDDO_REF
GND
32 31 30 29 28 27 26 25 VDD nPLL_SEL XTAL_IN XTAL_ OUT nXTAL _SEL CLK nCLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 VDDO_C QC
ICS8430S07I 32- Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
QD
VDDO_D
23 22
* * * * * *
Pin Assignment
CORE _SEL
21 GND 20 19 18 GND MR/ nOE_ REF
QB
17 VDDO_B
DDR_SEL1
DDR_SEL0
PCI_SEL1
nQA
QA
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PCI_SEL0
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VDDA
VDD
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Block Diagram
nPLL_SEL PD nXTAL_SEL PD
00 = 133.333MHz 01 = 100.000MHz 10 = 83.333MHz 11 = 125.000MHz DDR533, DDR400, or QA DDR667 Reference nQA Clock (LVPECL)
XTAL_IN
25MHz
XTAL_OUT
OSC
0 1
PLL
0 = 50.000MHz 1 = 33.333MHz
QB
Processor Core Clock (LVCMOS)
0 1
00 = 133.333MHz 01 = 100.000MHz 10 = 66.667MHz 11 = 33.333MHz 125MHz GbE CLK
CLK PD 25MHz nCLK PU/PD
QC
PCI or PCI-X Clock (LVCMOS) Gigabit Ethernet MAC Clock (LVCMOS)
QD
DDR_SEL1:0 PD CORE_SEL PD PCI_SEL1:0 PD MR/nOE_REF PD QREF0 Clock Output Control Logic
25MHz GbE CLK \ \ Gigabit Ethernet QREF1 / PHY Clocks / (LVCMOS) QREF2
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Table 1. Pin Descriptions
Number 1, 15 2 3, 4 5 6 7 8, 20, 21, 27 9, 10 11, 12 13, 14 16 17 18, 23, 26, 29, 30, 31 Name VDD nPLL_SEL XTAL_IN, XTAL_OUT nXTAL_SEL CLK nCLK GND PCI_SEL1, PCI_SEL0 DDR_SEL1, DDR_SEL0 nQA, QA VDDA VDDO_B QB, QC, QD, QREF2, QREF1, QREF0 Power Input Input Input Input Input Power Input Input Output Power Power Output Pulldown Pulldown Pulldown Pulldown Pullup/ Pulldown Pulldown Type Description Core supply pins. PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, bypasses the PLL. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when HIGH. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Internal resistor bias to VDD/2. Power supply ground. Selects the PCI/PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Analog supply pin. Bank B output supply pin. 3.3 V or 2.5V supply. Single-ended outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the QREF[2:0] outputs are in high impedance (HI-Z). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/ LVTTL interface levels. Selects the processor core clock output frequency. The output frequency is 50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. Bank C output supply pin. 3.3 V or 2.5V supply. Bank D output supply pin. 3.3 V or 2.5V supply. REF bank output supply pins. 3.3 V or 2.5V supply.
19
MR/nOE_REF
Input
Pulldown
22 24 25 28, 32
CORE_SEL VDDO_C VDDO_D VDDO_REF
Input Power Power Power
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor VDD, VDDO_X = 3.465V VDD = 3.465V, VDDO_X = 2.625V Test Conditions Minimum Typical 2 4 4 51 51 VDDO_X = 3.465V VDDO_X = 2.625V 15 20 Maximum Units pF pF pF k k
RPULLDOWN Input Pulldown Resistor QB, QC, QD, QREF[0:2] QB, QC, QD, QREF[0:2]

ROUT
Output Impedance
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
Function Tables
Table 3A. QB Output Control Input Function Table
Input CORE_SEL 0 (default) 1 Output Frequency QB 50MHz 33.333MHz
Table 3B. QA Output Control Input Function Table
Inputs DDR_SEL1 0 (default) 0 1 1 DDR_SEL0 0 (default) 1 0 1 Output Frequency QA, nQA 133.333MHz 100.000MHz 83.333MHz 125.000MHz
Table 3C. QC Output Control Input Function Table
Inputs PCI_SEL1 0 (default) 0 1 1 PCI_SEL0 0 (default) 1 0 1 Output Frequency QC 133.333MHz 100.000MHz 66.6667MHz 33.333MHz
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 50mA 100mA 39.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.20 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 170 20 25 Units V V V mA mA mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF. NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF.
Table 4B. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO_X = 2.5V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.20 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 VDD 2.625 160 20 20 Units V V V mA mA mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF. NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF.
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Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO_X = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 Units V V
IIH
Input High Current
VDD = VIN = 3.465V
150
A
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-10
A
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage: NOTE 1
VDDO_X = 3.465V VDDO_X = 2.625V VDDO_X = 3.465V or 2.625V
2.6 1.8 0.6
V V V
NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current nCLK Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 CLK/nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.15 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 Units A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VDD - 1.4 VDD - 2.0 0.55 Typical Maximum VDD - 0.8 VDD - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VDD - 2V.
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Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental 25 50 7 300 MHz Maximum Units
pF W
NOTE: Characterized using an 18pF parallel resonant crystal.
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AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V 5%, VDDO_X = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol Parameter QA/nQA QA/nQA QA/nQA QA/nQA QB fMAX Output Frequency QB QC QC QC QC QD QREF[0:2] tsk(b) tsk(pp) Bank Skew; NOTE 2, 4 Part-to-Part Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4, 5 Period Jitter (pk-pk); NOTE 4 Half-period Jitter (pk-pk) RMS Phase Jitter, (Random); NOTE 1 QREF[0:2] QREF[0:2] QB, QC, tjit(cc) QA/nQA QD tjit(per) tjit(hper) tjit(O) QA/nQA QA/nQA QREF[0:2] QD QB tR / tF Output Rise/Fall Time QA/nQA QC, QREF[0:2] QD QA/nQA odc Output Duty Cycle QB, QC, QD, QREF[0:2] 20% to 80% measured at crosspoint measured at crosspoint 25MHz (10kHz to 5MHz) 125MHz (1.875MHz to 20MHz) 100 100 100 100 49 45 -90 -90 0.73 0.78 450 300 450 450 51 55 measured at crosspoint Test Conditions DDR_SEL[1:0] = 00 DDR_SEL[1:0] = 01 DDR_SEL[1:0] = 10 DDR_SEL[1:0] = 11 CORE_SEL = 0 CORE_SEL = 1 PCI_SEL[1:0] = 00 PCI_SEL[1:0] = 01 PCI_SEL[1:0] = 10 PCI_SEL[1:0] = 11 Minimum Typical 133.333 100 83.333 125 50 33.333 133.333 100 66.667 33.333 125 25 35 400 270 95 200 90 90 Maximum Units MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ps ps ps ps ps ps ps ps ps ps ps ps ps % %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: All outputs running at corresponding fMAX.
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Typical Phase Noise at 125MHz (QD output @ 3.3V)
GbE Filter 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.78ps (typical) dBc Hz Noise Power Phase Noise Result by adding a GbE filter to raw data Offset Frequency (Hz)
Typical Phase Noise at 25MHz (QREF output @ 3.3V)
GbE Filter 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.73ps (typical)
Noise Power
dBc Hz
Raw Phase Noise Data
Offset Frequency (Hz)
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Phase Noise Result by adding a GbE filter to raw data 9

Raw Phase Noise Data
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ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information
2V 2V 1.65V5% 1.65V5%
VDD VDDA
Qx
SCOPE
VDD, VDDO_X VDDA
SCOPE
LVCMOS
Qx
LVPECL
nQx VEE
-1.65V5%
GND
-1.3V0.165V
3.3V Core/3.3V LVPECL Output Load AC Test Circuit
2.05V5% 1.25V5% 2.05V5% VDD VDDO_X
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
VDD
SCOPE
LVCMOS VDDA
GND Qx
nCLK
V
PP
Cross Points
V
CMR
CLK
GND
-
-1.25V5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
Differential Input Level
nQA QA
VOH VREF VOL
t half period n
1 fo
t jit(hper) = t half period n -- 1
Half Period Jitter
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t half period
n+1

2*fo Reference Point
(Trigger Edge)
t jit (pk-pk)
Histogram
Mean Period
(First edge after trigger) 10,000 cycles
Period Jitter
10
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ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information, continued
QREF[0:2]
VDDO_REF 2
Par t 1
Q_REFx
V
DDO_REF
2
QREF[0:2]
VDDO_REF 2 tsk(b)
Par t 2
Q_REFy
V
DDO_REF
2 tsk(pp)
LVCMOS Bank Skew
LVCMOS Part-to-Part Skew
nQA
V
QA QB:QD, QREF[0:2]
DDOX
V
DDOX
V
DDOX
2 tcycle n
2
2 tcycle n+1
tcycle n
tcycle n+1
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
LVPECL Cycle-to-Cycle Jitter
LVCMOS Cycle-to-Cycle Jitter
Phase Noise Plot Noise Power
nQA
80%
Phase Noise Mask
QA:QD, QREF[0:2]
20% tR tF
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Rise/Fall Time
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80% VSW I N G 20%
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information, continued
V
QB:QD, QREF[0:2]
DDOX
nQA QA
2
t PW
t
PERIOD
t PW
t
PERIOD
odc =
t PW t PERIOD
odc = x 100%
t PW t PERIOD
x 100%
LVCMOS Output Duty Cycle/Pulse Width/Period
LVPECL Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 1. Single-Ended Signal Driving Differential Input
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform ance, power supply isolation is required. The ICS8430S07I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs: CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs: LVPECL Outputs
The unused LVPECL output can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
Crystal Input Interface
The ICS8430S07I has been characterized with 18pF parallel resonant crystals. The capacitors C1 and C2 are not required, but can be populated for optimal ppm accuracy. The C1 and C2 values can be slightly adjusted to minimize ppm error for different board layouts.
XTAL_IN C1 Spare X1 18pF Parallel Crystal XTAL_OUT C2 Spare
Figure 4. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 5. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface
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Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output pair is low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 3.3V Zo = 50 + 3.3V
R3 125 Zo = 50
3.3V
R4 125
3.3V +
_ LVPECL Zo = 50 R1 50 RTT = 1 * Zo ((VOH + VOL) / (VCC - 2)) - 2 R2 50 VCC - 2V RTT Input LVPECL Zo = 50 R1 84 R2 84 _ Input
Figure 6A. 3.3V LVPECL Output Termination
Figure 6B. 3.3V LVPECL Output Termination
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 7. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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Application Schematic
Figure 8 shows a schematic example of using an ICS8430S07I. The crystal inputs are parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are optional. The tuning capacitor value can be slightly adjusted to optimize the frequency accuracy. This schematic example shows hardwired logic control input handling. The logic inputs can also be driven by 3.3V LVCMOS drivers. It is recommended to have one bypass capacitor per power pin. In general, the bypass capacitor values are ranged from 0.01uF to 0.1uF. Each bypass capacitor should be located as close as possible to the power pin. The low pass filter R6, C3 and C4 for clean analog supply should also be located as close to the VDDA pin as possible. Only two examples of LVPECL termination and one example of LVCMOS termination are shown in this schematic. Additional examples of LVPECL terminations and LVCMOS terminations can be found in the LVPECL Termination and LVCMOS Termination Application Notes.
Figure 8. ICS8430S07I Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8430S07I. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8430S07I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation * * Power (core)_MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (170mA + 20mA + 25mA) = 744.98mW Power (output)_MAX = 30mW/Loaded Output Pair
LVCMOS Output Power Dissipation * Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output * Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.7mW * 6 = 64.2mW
* Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.5mW per output
Total Power (25MHz) = 1.5mW * 3 = 4.5mW
*
Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 4pF * 133MHz * (3.465V)2 = 8mW per output
Total Power (133MHz) = 8mW * 3 = 24mW
Total Power Dissipation * Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (25MHz) + Total Power (125MHz) = 745mW + 30mW + 64.2mW + 4.5mW + 24mW = 867.7mW
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2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 39.5C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.868W * 39.5C/W = 119.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board.
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 39.5C/W 1 34.5C/W 2.5 31.0C/W
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3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL 50
VCC - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VDD - 2V. * For logic high, VOUT = VOH_MAX = VDD_MAX - 0.9V (VDD_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VDD_MAX - 1.7V (VDD_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VDD_MAX - 2V))/RL] * (VDD_MAX - VOH_MAX) = [(2V - (VDD_MAX - VOH_MAX))/RL] * (VDD_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VDD_MAX - 2V))/RL] * (VDD_MAX - VOL_MAX) = [(2V - (VDD_MAX - VOL_MAX))/RL] * (VDD_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 39.5C/W 1 34.5C/W 2.5 31.0C/W
Transistor Count
The transistor count for ICS8430S07I is: 10,871
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
To p View
Anvil Anvil Singulation Singula tion or OR Sawn Singulation
are Even
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
4 BB 2 1
CHAMFER
2 1 N N-1 AA 4 4
2 1
RADIUS
There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
CC
4
N N-1
4
DD 4
N N-1
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9.
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Ordering Information
Table 10. Ordering Information
Part/Order Number 8430S07AKILF 8430S07AKILFT Marking ICS30S07AIL ICS30S07AIL Package "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table Page 23 Description of Change Package Outline & Dimensions - added pin 1 indicator in package drawing. Date 9/3/09
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ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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Technical Support netcom@idt.com +480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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